#ifndef _CHIP_S3503_H_
#define _CHIP_S3503_H_

#define GPIO_REG                    0xb8000430  //gpio0 ~ gpio31
#define GPIOA_REG                   0xb8000434  //gpio32 ~ gpio63
#define GPIOB_REG                   0xb8000438  //gpio64 ~ gpio95
#define GPIOC_REG                   0xb800043c  //gpio96 ~ gpio127
#define GPIOD_REG                   0xb8000440  //gpio128 ~ gpio136

#define PIM_MUX_BASE                0xb8000000
#define PIN_MUX_REG_MASK            0xff000000
#define PIN_MUX_REG_SHIFT           24
#define PIN_BIT_HEIGHT_MASK         0x0000ff00
#define PIN_BIT_LOW_MASK            0x000000ff
#define PIN_BIT_HEIGHT_SHIFT        8
#define PIN_BIT_LOW_SHIFT           0

#define PIN_MUX_CTRL                (0x88 << PIN_MUX_REG_SHIFT)
#define PIN_MUX_CTRL1               (0x8C << PIN_MUX_REG_SHIFT)
#define PIN_MUX_CTRL2               (0xA4 << PIN_MUX_REG_SHIFT)
#define PIN_MUX_CTRL3               (0xA8 << PIN_MUX_REG_SHIFT)
#define PIN_MUX_CTRL4               (0xAC << PIN_MUX_REG_SHIFT)


//#define PIN_MUX_CTRL                (0xa8 << PIN_MUX_REG_SHIFT)
//#define PIN_MUX_CTRL1               (0xac << PIN_MUX_REG_SHIFT)

    
// Reg addr | reserved | end bit:bit_num<<8(bit8~15) | start bit:bit_num<<0(bit0~7)
#define DISEQC_OUT_SEL3				(PIN_MUX_CTRL | 31)
#define DISEQC_HV_SEL3				(PIN_MUX_CTRL | 30)
#define PK144_CA2_SEL1				(PIN_MUX_CTRL | 29)
#define SSI_SEL2					(PIN_MUX_CTRL | 28)
#define DISEQC_IN_SEL2				(PIN_MUX_CTRL | 27)
#define DISEQC_OUT_SEL2				(PIN_MUX_CTRL | 26)
#define DISEQC_HV_SEL2				(PIN_MUX_CTRL | 25)
#define PK144_UART_2TX_SEL			(PIN_MUX_CTRL | 24)
#define PK144_UART1_SEL				(PIN_MUX_CTRL | 23)
#define SSO_SEL						(PIN_MUX_CTRL | 22)
#define PK144_UART2_SEL				(PIN_MUX_CTRL | 21)
#define PK144_I2C3_SEL				(PIN_MUX_CTRL | 20)
#define PK256_CA1_SEL2				(PIN_MUX_CTRL | 19)
#define PK256_CA2_SEL2				(PIN_MUX_CTRL | 18)
#define SFLASH_FUNC_SEL				(PIN_MUX_CTRL | 17)
#define PK256_SQI_SEL				(PIN_MUX_CTRL | 16)
#define PK256_CA1_SEL1				(PIN_MUX_CTRL | 15)
#define PK256_UART_2TX_SEL			(PIN_MUX_CTRL | 14)
#define PK256_UART2_SEL				(PIN_MUX_CTRL | 13)
#define PK256_UART1_SEL				(PIN_MUX_CTRL | 12)
#define PK256_I2C2_SEL				(PIN_MUX_CTRL | 11)
#define PK144_CA2_SEL3				(PIN_MUX_CTRL | 10)
#define PK144_CA1_SEL3				(PIN_MUX_CTRL | 9)
#define STRAP_PIN_SEL_EN			(PIN_MUX_CTRL | 8)
#define RMII_SEL					(PIN_MUX_CTRL | 7)
#define I2C2_SEL					(PIN_MUX_CTRL | 6)
#define	HTPLG_SEL					(PIN_MUX_CTRL | 5)
#define SPDIF_SEL					(PIN_MUX_CTRL | 4)
#define PK256_SII2_SEL1				(PIN_MUX_CTRL | 3)
#define PK256_SSI_SEL1				(PIN_MUX_CTRL | 2)
#define PK256_SPI_SEL				(PIN_MUX_CTRL | 1)
#define PK256_CI_SEL				(PIN_MUX_CTRL | 0)


#define PKBGA_CI_SEL2				(PIN_MUX_CTRL1 | 31)
#define PK144_SQI_SEL				(PIN_MUX_CTRL1 | 30)
#define PK144_NFCEJ1_SEL			(PIN_MUX_CTRL1 | 29)
#define PK256_NFCEJ1_SEL			(PIN_MUX_CTRL1 | 28)
#define PK256_SPI_SEL2				(PIN_MUX_CTRL1 | 27)
#define REVERSE_RMII_SEL			(PIN_MUX_CTRL1 | 26)
#define QAM_TUN_AGC_SEL				(PIN_MUX_CTRL1 | 25)
#define QAM_IF_AGC_SEL				(PIN_MUX_CTRL1 | 24)
#define PKBGA_MMC_SEL				(PIN_MUX_CTRL1 | 23)
#define MCU_DEBUG_SYS_EN			(PIN_MUX_CTRL1 | 22)
#define NANDFLASH_CHIP_ENABLE_SEL	(PIN_MUX_CTRL1 | 21)
#define AUD_DDP_SPO_SEL				(PIN_MUX_CTRL1 | 20)
#define EMMC_FUNC_SEL				(PIN_MUX_CTRL1 | 19)
#define TEST_PIN_SEL				(PIN_MUX_CTRL1 | 18)
#define I2SO_SEL					(PIN_MUX_CTRL1 | 17)
#define ADAC_TEST_LRCLK_SEL			(PIN_MUX_CTRL1 | 16)
#define ADA_TEST_BCLK_SEL			(PIN_MUX_CTRL1 | 15)
#define ADAC_TEST_SDATA_SEL			(PIN_MUX_CTRL1 | 14)
#define VDATACR_SEL					(PIN_MUX_CTRL1 | 13)
#define VDATACB_SEL					(PIN_MUX_CTRL1 | 12)
#define VACTIVE_SEL					(PIN_MUX_CTRL1 | 11)
#define VDATAY_SEL					(PIN_MUX_CTRL1 | 10)
#define VCLK_SEL					(PIN_MUX_CTRL1 | 9)
#define VSYNC_SEL					(PIN_MUX_CTRL1 | 8)
#define HSYNC_sEL					(PIN_MUX_CTRL1 | 7)
#define VIN_SEL						(PIN_MUX_CTRL1 | 6)
#define PK256_SF_CSJ1_sEL			(PIN_MUX_CTRL1 | 5)
#define PK256_DISEQC_OUT_SEL		(PIN_MUX_CTRL1 | 4)
#define PK256_DISEQC_HV_SE			(PIN_MUX_CTRL1 | 3)
#define PK256_DISEQC_IN_SEL			(PIN_MUX_CTRL1 | 2)
#define RF_AGC_SEL					(PIN_MUX_CTRL1 | 1)
#define I2C1_SEL					(PIN_MUX_CTRL1 | 0)

#define NANDFLASH_FUNC_SEL			(PIN_MUX_CTRL2 | 31)
#define USB_RTD_SIG_SEL				(PIN_MUX_CTRL2 | 6)
#define AUD_DDP_SPO_EXT_SEL			(PIN_MUX_CTRL2 | 5)
#define SSO_SEL2					(PIN_MUX_CTRL2 | 4)
#define HDMI_TEST_RESEN_SEL			(PIN_MUX_CTRL2 | 3)
#define PK256_SSI2_SEL2				(PIN_MUX_CTRL2 | 2)
#define PK256_SPI_INV_SEL2			(PIN_MUX_CTRL2 | 1)
#define PK256_SPI_INV_sEL1			(PIN_MUX_CTRL2 | 0)

#define TEST_OUT_SEL				(PIN_MUX_CTRL3 | 8)
#define TEST_PIN_SEL3				(PIN_MUX_CTRL3 | 3)
#define TEST_PIN_SEL2				(PIN_MUX_CTRL3 | 2)
#define TEST_PIN_SEL1				(PIN_MUX_CTRL3 | 1)
#define TEST_PIN_SEL0				(PIN_MUX_CTRL3 | 0)


#define MAC_CLK_SEL					(PIN_MUX_CTRL4 | 24)
#define PHY_ADDR_4_MAC4				(PIN_MUX_CTRL4 | 20)
#define PHY_ADDR_4_MAC3				(PIN_MUX_CTRL4 | 19)
#define PHY_ADDR_4_MAC2				(PIN_MUX_CTRL4 | 18)
#define PHY_ADDR_4_MAC1				(PIN_MUX_CTRL4 | 17)
#define PHY_ADDR_4_MAC0				(PIN_MUX_CTRL4 | 16)





















#if 0
#define QAM128_ASSI_SEL					(PIN_MUX_CTRL | 30)
#define QAM128_SSI_SEL					(PIN_MUX_CTRL | 29)
#define REVERSE_RMII_SEL				(PIN_MUX_CTRL | 28)
#define RMII_SEL						(PIN_MUX_CTRL | 27)
#define SECOND_ASSI                     (PIN_MUX_CTRL | 26)
#define FIRST_ASSI                      (PIN_MUX_CTRL | 25)
#define SECOND_SSI                      (PIN_MUX_CTRL | 24)
#define FIRST_SSI                       (PIN_MUX_CTRL | 23)
#define SPI_SEL							(PIN_MUX_CTRL | 22)
#define PKG256_CA_SEL					(PIN_MUX_CTRL | 21)
#define SSO_SEL                        	(PIN_MUX_CTRL | 20)
#define PKG256_I2C3_SEL                 (PIN_MUX_CTRL | 19)
#define PKG256_UART_TX_SEL              (PIN_MUX_CTRL | 18)
#define PKQAM_XIFAGC_SEL              	(PIN_MUX_CTRL | 17)
#define PK256_XTUNAGC_SEL              	(PIN_MUX_CTRL | 16)
#define UART2_SEL              			(PIN_MUX_CTRL | 15)
#define I2C2_SEL              			(PIN_MUX_CTRL | 14)
#define PK256_UART_RX_SEL              	(PIN_MUX_CTRL | 13)
#define PKQAM_CA1_SEL              		(PIN_MUX_CTRL | 10)
#define SF128_SEL              			(PIN_MUX_CTRL | 9)

#define NF128_SEL		              	(PIN_MUX_CTRL | 7)
#define PK128_UART_RX_SEL              	(PIN_MUX_CTRL | 6)
#define PK128_UART_TX_SEL              	(PIN_MUX_CTRL | 5)
#define QAM256_DSUB_SEL              	(PIN_MUX_CTRL | 2)


#define MCU_DBG_EN                      (PIN_MUX_CTRL1 | 31)
#define NFLASH_CHIP_EN                  (PIN_MUX_CTRL1 | 21)
#define PK256_SECOND_XSPDIF_SEL         (PIN_MUX_CTRL1 | 19)
#define PK256_IRRX_SEL                  (PIN_MUX_CTRL1 | 18)
#define NMP144_DSUB_SEL                 (PIN_MUX_CTRL1 | 17)
#define AUD_DAC_TEST_SEL                (PIN_MUX_CTRL1 | 16)

#define QAM128_I2C4_sEL               	(PIN_MUX_CTRL1 | 15)
#define DDRPHY1_EJTAG_SEL               (PIN_MUX_CTRL1 | 14)
#define DDRPHY0_EJTAG_SEL               (PIN_MUX_CTRL1 | 13)
#define SWITCH_SPI_RMII_SEL             (PIN_MUX_CTRL1 | 12)

#define IHDMI_OP_RESEN_SEL              (PIN_MUX_CTRL1 | 11)
#define PK128_UART1_RX_AS_UART2_TX_SEL  (PIN_MUX_CTRL1 | 10)
#define PK256_UART1_RX_AS_UART2_TX_SEL  (PIN_MUX_CTRL1 | 9)
#define CI_ENABLE                    	(PIN_MUX_CTRL1 | 8)

#define PK128_I2C3_SEL                 	(PIN_MUX_CTRL1 | 7)
#define I2S_MCLK_SEL                    (PIN_MUX_CTRL1 | 6)
#define PK256_SPDIF_SEL                 (PIN_MUX_CTRL1 | 5)
#define I2C1_SEL                        (PIN_MUX_CTRL1 | 4)

#define HTPG_SEL                        (PIN_MUX_CTRL1 | 3)
#define PK256_I2SI_SEL					(PIN_MUX_CTRL1 | 2)
#define I2SO_SEL                 		(PIN_MUX_CTRL1 | 1)
#define PK128_SPDIF_SEL       			(PIN_MUX_CTRL1 | 0)
#endif



#endif

